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The ARM Cortex-A57 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline.〔(【引用サイトリンク】 title=Cortex-A57 Processor )〕 It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC). ==Overview== * Pipelined processor with deeply out of order, speculative issue 3-way superscalar execution pipeline * DSP and NEON SIMD extensions are mandatory per core * VFPv4 Floating Point Unit onboard (per core) * Hardware virtualization support * Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance. * TrustZone security extensions * Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution * 32 KiB data (2-way set-associative) + 48 KiB instruction (3-way set-associative) L1 cache per core * Integrated low-latency level-2 (16-way set-associative) cache controller, 512 KB, 1 MB, or 2 MB configurable size per cluster * 48-entry fully associative L1 instruction Translation Lookaside Buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes * * 4-way set-associative of 1024-entry L2 TLB * 2-level dynamic predictor with Branch Target Buffer (BTB) for fast target generation * Static branch predictor * Indirect predictor * Return stack 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「ARM Cortex-A57」の詳細全文を読む スポンサード リンク
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